The Ethernet PHY doubles the bandwidth of routers and line cards | 黑森爾電子
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The Ethernet PHY doubles the bandwidth of routers and line cards

Technology Cover
發佈日期: 2022-03-01, Microchip Technology

     Routers, switches, and line cards require higher bandwidths, port densities, and connections of up to 800GbE to handle escalating data center traffic driven by 5G, cloud services, AI, and ML applications. These challenges can now be overcome with what Microchip Technology calls the industry's most compact 1.6T low-power PHY solution, with the PM6200 Meta-DX2L reducing power per port by 35% compared to the 56G PAM4 predecessor meta-DX1, The META-DX1 is the industry's first terabyte PHY solution. Also to provide higher bandwidth, these designs must overcome the signal integrity challenges posed by the industry's transition to 112G PAM4 SerDes connections to support the latest pluggable optical systems, system backplanes, and packet processors

      Bob Wheeler, principal network analyst at The Linley Group said:"The industry is transitioning to The 112G PAM4 ecosystem for high-density switching, packet processing and optics,"  "Microchip's META-DX2L is optimized for 100GBE, 400GBE, and 800GBE connections through bridge wiring cards and multi-rate optical switching to meet these needs."

     PHY's low-power PAM4 SerDes enable it to support the next generation infrastructure interface rates of cloud data centers, AI/ML computing clusters, 5G and telecom service provider infrastructures, whether through long-distance DAC cables, backplane, or connectivity to pluggable optics. Featuring high-density 1.6T bandwidth, saving space footprint, 112G PAM4 SerDes technology, and supporting Ethernet rates from 1GbE to 800GbE, the Ethernet PHY is an industrial temperature class device that provides connectivity versatility and maximizes design reuse, from retimer, Transmission or reverse transmission to a collision-free 2:1 multiway. Highly configurable intersections and transmission features take full advantage of the SWITCH device's I/O bandwidth to facilitate flexible connections required for multi-rate cards that support a wide range of pluggable optics.

    Babak Samimi, vice president of Microchip's communications business saidt:"For the 56G generation, we launched the industry's first terabit physical layer, meta-DX1, and now we're rolling out an equally transformative 112G solution that enables systems developers to address today's cloud data centers, 5G networks, and AI/ML computing lateral scaling,"  "By delivering up to 1.6 TERabytes of bandwidth in a low-power architecture with minimal occupying area, the META-DX2L PHY doubles the bandwidth of previous solutions on the market while establishing new levels of energy efficiency."

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